1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same, in particular to, a semiconductor device having a semiconductor substrate, on which both of a memory device and a logic device are formed, hereinbelow referred to as a logic process consolidating device, and a method of producing the semiconductor device.
2. Discussion of Background
In recent years, it is required that semiconductor devices are formed to be a single chip in response to an age of multimedia. For example, a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory, and a logic device are formed on a single semiconductor substrate and mounted on a single chip.
FIG. 24 is a cross-sectional view illustrating a structure of a conventional logic process consolidating DRAM. In FIG. 24, numerical reference 100 designates a memory device region; and numerical reference 101 designates a logic device region. Hereinbelow, the structure of the conventional logic process consolidating DRAM will be described in reference of FIG. 24.
A cross-sectional structure of the memory device region of the conventional logic process consolidation DRAM will be described. In the memory device region, an active region formed by a bottom n-well 52 and a p-well region 53a formed on a bottom n-well 52 is located on a silicon substrate 51. On a principle surface of the silicon substrate 51, an isolating region 54 and a gate oxide film 55 are formed. On the p-well region 53a surrounded by the isolating region 54 has source/drain areas 56a, 56b. 
On the gate oxide film 55 and an isolating oxide film 54, gate electrodes 57a through 57c are formed with a predetermined interval. On upper surfaces of the gate electrodes 57a through 57c, for example, an insulating film 58 made of a silicon nitride film or a TEOS oxide film is formed. Further, a silicon oxide film 59 is formed on the insulating film 58, the source/drain areas 56a, 56b, and the isolating region 54 so as to cover these. A silicon nitride film 60 is formed so as to cover an upper surface of the silicon oxide film 59. Further, an inter-layer insulating film 67 is formed to cover the silicon nitride film 60.
Above the source/drain area 56b, the inter-layer insulating film 67, the silicon nitride film 60, the silicon oxide film 59, a part of the insulating film 58 formed on the gate electrodes 57b and 57c, and a self-alignment contact opening 69 for exposing the gate oxide film 55 are formed. The self-alignment contact opening 69 is formed to expose a surface of the source/drain area 56b. 
A plug made of a conductive material and so on is formed in the self-alignment contact opening 69. Such a plug is used as a contact for, for example, a storage node contact of a bit wire or a capacitor cell. After forming the plug, a lower electrode (not shown) of a bit wire or a capacitor is formed. The lower electrode of a bit wire or the capacitor is electrically connected to the source/drain area 56b through the plug.
Meanwhile, in the logic device region, the isolating region 54 is formed on a principle surface of the silicon substrate 51. Further, on the active region surrounded by the isolating region 54, the n-well region 53b and the p-well region 53c are respectively formed. In the n-well region 53b, low concentration impurity regions 56c, 56d and high concentration impurity regions 62c, 62d are formed, whereby source/drain regions 70c, 70d having a lightly doped drain (LDD) structure are configurated.
Further, in the p-well region 53c of the silicon substrate 51, low concentration impurity regions 56e, 56f and high concentration impurity regions 62a, 62b are formed, whereby source/drain areas 70a, 70b having a LDD structure are configurated. On a channel region between source/drain areas 70c and 70d, a gate electrode 57d is formed through a gate oxide film 55. Further, in the p-well region 53c, a gate electrode 57e is formed through the gate oxide film 55.
The insulating film 58 made of a silicon nitride film or a TEOS oxide film is formed respectively on upper surfaces of the gate electrodes 57d and 57e. A side wall made of the silicon oxide film 59 and the silicon nitride film 60 is formed so as to be in contact with side surfaces of the gate electrode 57d and the insulating film 58. In a similar manner, a side wall made of the silicon oxide film 59 and the silicon nitride film 60 is formed so as to be in contact with side surfaces of the gate electrode 57e and the insulating film 58.
A silicide protection film 64 is formed to cover parts respectively of the insulating film 58 formed on the upper surface of the gate electrode 57d, a surface of the side wall, and the source/drain areas 62c, 62d. On the source/drain areas 70a through 70d without the silicide protection film 64, a high-melting metallic silicide film 66 made of, for example, a cobalt silicide film, a titanium silicide film, and so on is formed. The inter-layer insulating film 67 is formed above an entire surface of the semiconductor substrate 51.
In the conventional logic process consolidating device, a conduction type of the active region and a conduction type of the impurities to be implanted are not limited to those described above, and adverse conduction types may be used.
In the next, in reference of FIGS. 13 through 24, a method of producing the conventional logic process consolidating device will be described. In FIG. 13, the isolating region 54 is formed on the principle surface of the silicon substrate 51, in which the bottom n-well 52, the p-well region 53a, the n-well region 53b and the p-well region 53c are formed. A structure of isolating of the isolating region 54 is obtained by opening a deep groove in the silicon substrate 51, and embedding an insulating film such as an oxide film in use of a Shallow Trench Isolation (STI) process, whereby the structure of isolation becomes flat.
The gate oxide film 55 is formed on the principle surface of the silicon substrate 51. In a predetermined area on the gate oxide film 55 or the isolating oxide film 54, the gate electrodes 57a through 57e are formed. An n-type impurity is implanted in the p-well regions 53a, 53c in the silicon substrate 51 by ion implantation. A p-type impurity is implanted in the n-well 53b in the silicon substrate 51 by ion implantation. Thus, the source/drain areas 56a, 56b and the low concentration impurity regions 56c through 56f are formed. As illustrated in FIG. 14, the silicon oxide film 59 is formed above the entire surface of the silicon substrate 51 so as to cover the gate electrodes 57a through 57e and the insulating film 58 formed thereon. The silicon nitride film 60 is formed on the silicon oxide film 59. As illustrated in FIG. 15, a resist 61 is coated, and an n-type transistor area in the logic device region is opened by photoengraving.
In the next, the silicon oxide film 59 and the silicon nitride film 60 are subjected to anisotropic etching to form side walls on both sides of the gate electrode 57e. An n-type impurity is further implanted in a self-replicating manner using the side walls and so on as a mask to form the high concentration impurity regions 62a, 62b. The source/drain area 70a having the LDD structure is configurated by the low concentration impurity region 56e and the high concentration impurity region 62a. Further, the source/drain area 70b having the LDD structure is configurated by the low concentration impurity region 56f and the high concentration impurity region 62b. 
As illustrated in FIG. 16, the resist 63 is coated, and the p-type transistor region in the logic device region is opened by photoengraving. Succeedingly, the silicon oxide film 59 and the silicon nitride film 60 are subjected to anisotropic etching to form side walls on both sides of the gate electrode 57d. A p-type impurity is further implanted in a self-replicating manner using the side walls and so on as a mask to form the high concentration impurity regions 62c, 62d. The source/drain area 70c having the LDD structure is configurated by the low concentration impurity region 56c and the high concentration impurity region 62c. The source/drain area 70d having the LDD structure is configurated by the low concentration impurity region 56d and the high concentration impurity region 62d. 
After removing the resist 63, a silicon oxide film 64 is formed above an entire surface of the silicon substrate 51 to be served as a silicide protection film in the logic device as illustrated in FIG. 17. In the next, a resist is coated, and a resist pattern 65 is formed by photoengraving as illustrated in FIG. 18. Further, the silicon oxide film 64 is subjected to anisotropic etching using the resist pattern 65 as a mask, whereby the resist pattern 65 is removed as illustrated in FIG. 19. As illustrated in FIG. 20, the high melting point metal silicide film 66 is formed on surfaces of the source/drain areas 70a through 70d externally exposed.
As illustrated in FIG. 21, the inter-layer insulating film 67 is formed above the entire surface of the silicon substrate 51. As illustrated in FIG. 22, a resist 68 is coated, and the resist above the source/drain area 56b in the memory device region is patterned by photoengraving. As illustrated in FIG. 23, the inter-layer insulating film 67 is subjected to anisotropic etching using the resist 68 as a mask and using the silicon nitride film 60 as an etching stopper.
Then, the resist 68 is removed. As illustrated in FIG. 24, the silicon nitride film 60, the silicon oxide film 59, and the insulating film 58 are subjected to anisotropic etching in a self-replicating manner to expose the source/drain area 56b. Thus, the self-alignment contact opening 69 is formed.
FIGS. 25 through 30 are cross-sectional views for illustrating a structure of the conventional logic process consolidating device, wherein problems in steps after the step illustrated in FIG. 18 are explained. Processes of the method of producing the device will be briefly described in reference of FIGS. 25 through 30. As illustrated in FIG. 18, in the conventional logic process consolidating device, a silicide protection film 64 is formed even in a memory device region, in which the silicide protection film 64 is unnecessary. As illustrated in FIG. 25, the silicide protection film 64 is etched using a resist pattern 65 as a mask. As illustrated in FIG. 26, a high-melting metallic silicide film 66 is formed on exposing surfaces of source/drain areas 70a through 70d. 
As illustrated in FIG. 27, an inter-layer insulating film 67 is formed above an entire surface of a silicon substrate 51. Thereafter, as illustrated in FIG. 28, a resist 68 is coated, and a part of the resist above a source/drain area 56b in the memory device region is patterned by photoengraving. As illustrated in FIG. 29, the inter-layer insulating film 67 is subjected to anisotropic etching using the resist 68 as a mask and a silicon nitride film 60 as an etching stopper. The resist 68 is removed. As illustrated in FIG. 30, the silicon nitride film 60, a silicon oxide film 59, and an insulating film 58 are subjected to anisotropic etching in a self-replicating manner to expose the source/drain area 56b, whereby a self-alignment contact opening 69 is formed.
As illustrated in FIG. 25, in the conventional logic process consolidating device, the silicon nitride film 60 above gate electrodes 57a through 57c is etched as a result of over-etching, which occurs at time of etching the silicide protection film 64 in the memory device region. Therefore, any etching stopper does not exist above the source/drain area 56b, whereby there is a possibility that the gate electrode is exposed at time of forming the self-alignment contact opening 69. When the gate electrode is exposed, there is a problem that a wiring layer such as a bit wire formed after forming the self-alignment contact opening 69 is shorted with the gate electrode, wherein reliability of the semiconductor device is deteriorated.
Meanwhile, as illustrated in FIG. 25, it is difficult to etch the silicide protection film 64 between the gate electrodes to completely remove this because an aspect ratio between the gate electrodes is high. Thus the silicide protection film 64 is left between the gate electrodes. The aspect ratio between the gate electrodes are further increased by the remaining silicide protection film 64. As a result, as illustrated in FIG. 27, the inter-layer insulating film 67 is not formed between the gate electrodes at time of forming the inter-layer insulating film 67 made of BPSG and so on, whereby a cavity is formed therein. Accordingly, there is a problem that transistors are not securely insulated, wherein reliability of the semiconductor device is deteriorated.
Further, because the remaining silicide protection film 64 left at time of etching the inter-layer insulating film 67 in steps illustrated in FIGS. 28 and 29 is hardly etched since the remaining silicide protection film 64 does not contain boron or phosphorous. Thus, the remaining silicide protection film 64 is left between the gate electrodes 57b, 57c and a hole. Accordingly, there are problems that the aspect ratio of the self-alignment contact opening 69 is increased as illustrated in FIG. 30, and it becomes difficult to connect a wiring layer formed after forming the self-alignment contact opening 69 to the source/drain area 56b in the silicon substrate 51.
Further, in the logic process consolidating device, because there are processes for all of devices integrated in the logic process consolidating device and processes for a single device, the number of steps for forming the logic process consolidating device is increased, wherein the producing process is in tendency of complicating.
It is an object of the present invention to solve the above-mentioned problems in the conventional logic process consolidating device and to provide a semiconductor device having different devices on one semiconductor substrate, namely a logic process consolidating device, and a method of producing the semiconductor device without complicating a production process.
According to a first aspect of the present invention, there is provided a semiconductor device having a memory device region (100) and a logic device region (101) on a principle surface of a semiconductor substrate comprising:
a pair of first and second source/drain areas (6a, 6b) formed with an interval so as to sandwich a first channel region (3a) on a principle surface of the memory device region (100);
a pair of first and second low concentration impurity regions (6c, 6d) formed with intervals so as to sandwich a second channel region (3b) on a principle surface of the logic device region;
a first gate electrode (7b) and a second gate electrode (7d) formed on a gate oxide film (5) respectively formed on the first channel region (3a) and second channel region (3b);
a silicon oxide film (9) formed so as to cover the first gate electrode (7b) and the second gate electrode (7d);
a silicon nitride film (10) formed on the silicon oxide film (9);
an inter-layer insulating film (15) formed on the silicon nitride film (10);
a self-alignment contact opening (17) formed in an area above the first source/drain area (6b) of the inter-layer insulating film (15), the silicon nitride film (10), and the silicon oxide film (9) formed on the memory device area (100);
a side wall film made of the silicon oxide film (9) and the silicon nitride film (10) extending through areas above the first and the second low concentration impurity regions (6c, 6d) so as to cover an upper portion and a side wall of the second gate electrode (7d); and
first and second high concentration impurity regions (12c, 12d) formed from ends of the side wall film on the semiconductor substrate (1).
According to a second aspect of the present invention, there is provided the semiconductor device,
wherein the silicon oxide film (9) and the silicon 25 nitride film (10) formed on the upper portion and the side surface of the second gate electrode (7d) in the logic device region (101) have a function as a silicide protection film in addition to a function as the side wall film for the second gate electrode (7d).
According to a third aspect of the present invention, there is provided a method of producing a semiconductor device having a memory device region (100) and a logic device region (101) on a principle surface of a semiconductor substrate (1) comprising steps of:
forming a pair of first and second source/drain areas (6a, 6b) with an interval so as to sandwich a first channel region (3a) on the memory device region (100) and a pair of first and second low concentration impurity regions (6e, 6f) with an interval so as to sandwich a second channel region (3c) in the logic device region (101);
forming a first gate electrode (7b) and a second gate electrode (7e) on gate oxide films (5) respectively above the first channel region (3a) and the second channel region (3c);
forming a silicon oxide film (9) on the semiconductor substrate (1) so as to cover the first gate electrode (7b) and the second gate electrode (7e);
forming a silicon nitride film (10) on the silicon oxide film (9);
coating a resist (11) on an upper portion of the second gate electrode (7e) and providing the silicon oxide film (9) and the silicon nitride film (10) with anisotropic etching using the resist as a mask; and
implanting impurity ions into the semiconductor substrate (1) in a self-replicating manner using the resist (11), the silicon oxide film (9), and the silicon nitride film (10) as a mask to form first and second high concentration impurity regions (12a, 12b).
According to a fourth aspect of the present invention, there is provided the method of producing the semiconductor device further comprising steps of:
forming a high-melting metallic silicide film (14) on surfaces of the first and second high concentration impurity regions (12a, 12b) after the step of forming the first and second high concentration impurity regions (12a, 12b).
According to a sixth aspect of the present invention, there is provided the method of producing the semiconductor device further comprising steps of:
forming an inter-layer insulating film (15) on an entire surface of the semiconductor substrate (1) after the step of forming the high-melting point metallic silicide film (14); and
forming a self-alignment contact opening (17) in a region positioned above the first source/drain area (6b) of the inter-layer insulating film (15), the silicon nitride film (10), and the silicon oxide film (9) formed in the memory device region (100).
According to a seventh aspect of the present invention, there is provided the method of producing the semiconductor device,
wherein the step of forming the self-alignment contact opening (17) comprising steps of:
forming a first opening by etching the inter-layer insulating film (15) above the first source/drain area (6b) using the silicon nitride film (10) as an etching stopper film; and
forming a second opening reaching the first source/drain area (6b) by etching the silicon nitride film (10) and the silicon oxide film (9) inside the first opening.